Design of Low Power CMOS Low Noise Amplifier Using Current Reuse Technique

被引：0

作者：

Sathwara, Hardik ^{[1
]}

Shah, Kehul ^{[1
]}

机构：

[1] Sankalchand Patel Coll Engn, Dept E&C, Visnagar, Gujarat, India

来源：

2015 5TH NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE) | 2015年

关键词：

Current reuse method; Low power; LNA; Wideband;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S-21) of 7.5 dB and input return loss (S-11) of -14 dB. All simulations are performed by using EDA Tanner T-Spice and ADS 2011.10 tools.

引用

页数：6

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