Voltage-pulse driven harmonic resonant rail drivers for low-power applications

被引:1
|
作者
Moon, JS
Athas, WC
Soli, SD
Draper, JT
Beerel, PA
机构
[1] Univ So Calif, Inst Informat Sci, Marina Del Rey, CA 90292 USA
[2] House Ear Res Inst, Los Angeles, CA 90057 USA
[3] Univ So Calif, Los Angeles, CA 90089 USA
关键词
clock generator; energy-recovery circuit; harmonic resonance; low power;
D O I
10.1109/TVLSI.2003.814323
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC(L)V(2) at 15 MHz and 97.8 pF load.
引用
收藏
页码:762 / 777
页数:16
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