On implementation aspects of fast iterative tap amplitude and delay estimation for UMTS/WCDMA

This communication discusses implementation aspects of a novel, fast iterative tap amplitude and delay estimation (ITADE) technique for RAKE receivers required for the downlink in the universal mobile telecommunications system (UNITS) frequency domain duplex (FDD) mode wideband code division multiple access (WCDMA). The Texas Instruments TMS320C6416 digital signal processor (DSP), operating at 720 MHz clock rate, is taken as the target hardware. The manuscript shall primarily focus on a sliding correlation-based ITADE algorithm developed by the authors. This algorithm shall be abbreviated by CITADE. The implementation of the CITADE algorithm exploits both the hierarchical structure of the primary synchronisation channel code, which is used as a reference for the TADE strategy, and the tailored instructions of the TMS320C6416 DSP. The found implementation requires 809 kilocycles or, equivalently, similar or equal to 1.1 ins of processing time. This processing time corresponds to a duration of similar or equal to 1.7 time slots. The presented proposal is considered a competitive design with a better performance regarding the number of required processor cycles compared to previously published work.