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- [1] A Simulation Study for Typical Design Rule Patterns and Stochastic Printing Failures in a 5 nm Logic Process with EUV Lithography 2020 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2020 (CSTIC 2020), 2020,
- [2] A STUDY OF THE VIA PATTERN LITHOGRAPHY PROCESS WINDOW UNDER THE 7 NM LOGIC DESIGN RULES WITH 193 NM IMMERSION LITHOGRAPHY CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,