Implementation of precise exception in a 5-stage pipeline embedded processor

An exception is precise if the saved processor state corresponds with the sequential model of program execution where one instruction completes before the next begins. In a pipelined processor, precise exception is difficult to achieve because an instruction must pass several stages before it modifies the processor's state and many instructions are simultaneously being processed in the different phases of the execution. In this paper, an approach is provided to implement the 5-stage pipeline RISC processor precise exception in details.