Hardware Demonstration of a Novel Three-Phase Multilevel Inverter

被引:0
|
作者
Chen, Tuofei [1 ]
Gu, Lei [1 ]
Dally, William [1 ]
Fox, John [2 ]
机构
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[2] Stanford Univ, Dept Appl Phys, Stanford, CA USA
关键词
Multi-level inverter; three-phase; high-efficiency; DC-link capacitance; CONVERTER; DC;
D O I
10.1109/ECCE50734.2022.9947528
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
We present the hardware design of a novel three-phase multilevel inverter (MLI) for PV applications. The advantage of the proposed MLI is two-fold: 1) it does not require large DC-link capacitors to buffer the 120 Hz power ripple and 2) it allows individual inverter module to output a trapezoidal power waveform instead of a sinusoidal power waveform. The trapezoidal operation enables inverter module to process peak or zero power for most of the AC cycle and increase the overall DC-AC efficiency. This new design features two inverters connected in parallel to each DC source and N inverters connected in series to each grid phase to support the grid voltage. An experimental 100V DC input, 120V(rms) AC output, 1kW 2-level prototype with > 95% efficiency has been built to verify the proposed design. With the same inverter module, we compare the efficiency of the proposed design to that of the conventional MLI design where all modules share phase power equally. We demonstrate that the proposed design consistently outperforms the conventional design in efficiency at all power levels, with > 20% loss reduction at light load conditions.
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页数:7
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