Interconnect capacitance extraction in large-area a-Si imaging systems

We present a new numerical extraction method for the quasi-static parasitic coupling capacitances associated with geometric overlapping in amorphous silicon (a-Si) thin film transistors (TFTs) and interconnect addressing lines in large-area a-Si imaging systems. The capacitance is extracted using a recently developed computational technique, based on exponential expansion of the Green's function, which offers a quick and accurate means of computing the three-dimensional potential and electric field, and hence, the charge distribution and capacitance. The technique can be used for effectively dealing with the extreme geometry TFT and interconnect structures (where layer thicknesses are much smaller than the other physical dimensions), the floating potential of the glass substrate, and multi-dielectric media, all of which are typical to large-area a-Si imaging electronics.