Architectural Support for Efficient Large-Scale Automata Processing

被引:0
|
作者
Liu, Hongyuan [1 ]
Ibrahim, Mohamed [1 ]
Kayiran, Onur [2 ]
Pai, Sreepathi [3 ]
Jog, Adwait [1 ]
机构
[1] Coll William & Mary, Williamsburg, VA 23187 USA
[2] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
[3] Univ Rochester, Rochester, NY 14627 USA
基金
美国国家科学基金会;
关键词
D O I
10.1109/MICR0.2018.00078
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The Automata Processor (AP) accelerates applications from domains ranging from machine learning to genomics. However, as a spatial architecture, it is unable to handle larger automata programs without repeated reconfiguration and re execution. To achieve high throughput, this paper proposes for the first time architectural support for AP to efficiently execute large-scale applications. We find that a large number of existing and new Non-deterministic Finite Automata (NFA) based applications have states that are never enabled but are still configured on the AP chips leading to their underutilization. With the help of careful characterization and profiling-based mechanisms, we predict which states are never enabled and hence need not be configured on AP. Furthermore, we develop SparseAP, a new execution mode for AP to efficiently handle the mis-predicted NFA states. Our detailed simulations across 26 applications from various domains show that our newly proposed execution model for AP can obtain 2.1x geometric mean speedup (up to 47x) over the baseline AP execution.
引用
收藏
页码:908 / 920
页数:13
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