A SAT method for improving test pattern generation

被引:0
|
作者
Liu Xin [1 ]
Xiong Youlun [2 ]
机构
[1] Hubei Univ Technol, Sch Elect & Elect Engn, Wuhan 430068, Peoples R China
[2] Huazhong Univ Sci & Technol, Sch Mech Sci & Engn, Wuhan 430074, Peoples R China
基金
中国国家自然科学基金;
关键词
test pattern generation; fault detection; Boolean satisfiability; BDD;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:398 / 403
页数:6
相关论文
共 50 条
  • [1] Enhancing SAT-Based Test Pattern Generation
    刘歆
    熊有伦
    Journal of Electronic Science and Technology, 2005, (02) : 134 - 139
  • [2] Improving test pattern compactness in SAT-based ATPG
    Eggersgluess, Stephan
    Drechsler, Rolf
    PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 445 - 450
  • [3] Techniques for SAT-based constrained test pattern generation
    Balcarek, Jiri
    Fiser, Petr
    Schmidt, Jan
    MICROPROCESSORS AND MICROSYSTEMS, 2013, 37 (02) : 185 - 195
  • [4] SAT-Based Test Pattern Generation with Improved Dynamic Compaction
    Czutro, Alexander
    Redddy, Sudhakar M.
    Polian, Ilia
    Becker, Bernd
    2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014), 2014, : 56 - 61
  • [5] Improving Test Pattern Generation with Implication Learning
    Liu Xin
    2011 2ND INTERNATIONAL CONFERENCE ON CHALLENGES IN ENVIRONMENTAL SCIENCE AND COMPUTER ENGINEERING (CESCE 2011), VOL 11, PT A, 2011, 11 : 125 - 131
  • [6] PASSAT:: Efficient SAT-based test pattern generation for industrial circuits
    Shi, J
    Fey, G
    Drechsler, R
    Glowatz, A
    Hapke, F
    Schlöffel, J
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN, 2005, : 212 - 217
  • [7] Experimental studies on SAT-based test pattern generation for industrial circuits
    Shi, JH
    Fey, G
    Drechsler, R
    Glowatz, A
    Schlöffel, J
    Hapke, F
    2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 967 - 970
  • [8] A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking
    Zhong, Yadi
    Guin, Ujjwal
    IEEE TRANSACTIONS ON COMPUTERS, 2023, 72 (08) : 2293 - 2305
  • [9] Improving algorithm for test pattern generation using satisfiability
    Zeng, Chengbi
    Chen, Guangju
    Chengdu Kejidaxue Xuebao/Journal of Chengdu University of Science and Technology, 2000, 32 (03): : 54 - 57
  • [10] A Test Sequence Generation Method for Communication Protocols Using the SAT Algorithm
    Mori, Takanori
    Otsuka, Hirotaka
    Funabiki, Nobuo
    Nakata, Akio
    Higashino, Teruo
    Systems and Computers in Japan, 2003, 34 (11) : 20 - 29