An FPGA Compatible Asynchronous Wake-Up Receiver for Wireless Sensor Networks

This paper explores design methods applicable to Wireless Sensors Networks, where low power consumption and energy efficiency are a must. A key component that modulates the power consumption is the main radio. Controlling its use through suitable sleep modes and wake up mechanisms is a significant issue and can be done with a wake-up receiver. But many applications are associated with low fabrication volume where custom integrated circuits are not economical and where FPGAs are the best available solution. In this paper, we explore an asynchronous solution, which permits to decrease the internal activity, thus reducing the power consumption, including that required for clock distribution. We also propose an FPGA implementation of such a wake-up receiver using the NULL Convention Logic T. The overall power consumption of the reported implementation is as low as 5 mu W at 250 kbps.