Reliability investigations of flip-chip solder bumps on palladium

被引:0
|
作者
Kallmayer, C [1 ]
Oppermann, H [1 ]
Anhöck, S [1 ]
Klein, M [1 ]
Kalicki, R [1 ]
Aschenbrenner, R [1 ]
Reichl, H [1 ]
机构
[1] Fraunhofer IZM, D-13355 Berlin, Germany
关键词
D O I
10.1109/ECTC.1999.776161
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The choice of the solder joint metallurgy is a key issue especially for the reliability of flip chip assemblies. Besides the systems which are already widely used and well understood, new materials are emerging as solderable under bump metallizations (UBMs). Palladium can be used as a basis for flip chip bumps in different ways: For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if the dies are not available on wafer level and the chosen assembly technology is flip chip soldering. On wafer level electroless deposition of Palladium bumps is available on which solder can be deposited e.g, by stencil printing or meniscus bumping. The scope of this paper is to summarize the results from aging of eutectic Pb/Sn solder on Palladium stud bumps. The intermetallic growth which is observed and its impact on the mechanical and electrical reliability are investigated. Based on this data Palladium as an under bump metallization can be compared to alternative materials such as Nickel.
引用
收藏
页码:135 / 140
页数:6
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