0.5 V CMOS inverter-based tunable transconductor

被引：27

作者：

Vlassis, S. ^{[1
]}

机构：

[1] Univ Patras, Dept Phys, Elect Lab, Patras 26504, Greece

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2012年 / 72卷 / 01期

关键词：

Analog circuits; Tunable circuits; CMOS transconductors; FILTER; DESIGN;

D O I：

10.1007/s10470-012-9865-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master-slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 mu m CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 mu A current consumption.

引用

页码：289 / 292

页数：4

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