Design of Multimedia SoC Platform with a Crossbar On-chip Bus for Embedded Systems

被引:0
|
作者
Jung, Hongkyun [1 ]
Jin, Xianzhe [1 ]
Jung, Younjin [1 ]
Kim, Ok [1 ]
Lee, Byoungyup [1 ]
Heo, Jungbum [1 ]
Ryoo, Kwangki [1 ]
机构
[1] Hanbat Natl Univ, Grad Sch Informat & Commun, Taejon, South Korea
关键词
D O I
10.1109/NCM.2008.250
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DAM, AC97 controller, debug interface and UART The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. As a result of the test program, the proposed platform has better efficiency by 2658% than the SoC platform with shared bus on-chip bus.
引用
收藏
页码:292 / 297
页数:6
相关论文
共 50 条
  • [1] On-Chip Bus Design for HDTV SoC Decoder
    Yi Zhiqiang
    Li Yun
    2010 6TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS NETWORKING AND MOBILE COMPUTING (WICOM), 2010,
  • [2] On-chip cache algorithm design for multimedia SOC
    Pratoomtong, A
    Hu, YH
    2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING, 2005, : 337 - 340
  • [3] On compliance test of on-chip bus for SOC
    Lin, HM
    Yen, CC
    Shih, CH
    Jou, JY
    ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 328 - 333
  • [4] An Analytical Model for On-Chip Interconnects in Multimedia Embedded Systems
    Wu, Yulei
    Min, Geyong
    Zhu, Dakai
    Yang, Laurence T.
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2013, 13
  • [5] Power evaluation of the arbitration policy for different on-chip bus based SoC platform
    Srinivasan, Prakash
    Ahmadinia, Ali
    Erdogan, Ahmet T.
    Arslan, Tughrul
    20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 159 - 162
  • [6] Fraction Control Bus: A new SOC on-chip communication architecture design
    Wang, N
    Bayoumi, MA
    ESA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS, 2005, : 124 - 129
  • [7] On-chip bus architecture optimization for multi-core SoC systems
    Lien, Cheng-Min
    Chen, Ya-Shu
    Shih, Chi-Sheng
    SOFTWARE TECHNOLOGIES FOR EMBEDDED AND UBIQUITOUS SYSTEMS, 2007, 4761 : 301 - +
  • [8] Embedded firewall for on-chip bus transactions
    Lazaro, Jesus
    Bidarte, Unai
    Muguira, Leire
    Astarloa, Armando
    Jimenez, Jaime
    COMPUTERS & ELECTRICAL ENGINEERING, 2022, 98
  • [9] Reconfigurable on-chip interconnection networks for high performance embedded SoC design
    Oveis-Gharan, Masoud
    Khan, Gul N.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2020, 106
  • [10] Dynamic fraction control bus: New SOC on-chip communication architecture design
    Wang, N
    Bayoumi, MA
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2005, : 199 - 202