Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops

Negative bias temperature instability is an important reliability issue for FinFET and gate-all-around nanowire FETs at next-generation technology nodes which leads to circuit failure during the life time of the device. This paper compares the performance parameters of widely used FinFET and gate-all-around flip-flop structures through HSPICE at V-DD=0.7V to show the power and PDP superiority of gate-all-around flip-flops. Furthermore, the NBTI degradation analysis of FinFET and gate-all-around flip-flops is conducted by MOSRA simulation. The reliability analyses demonstrate that the performance degradation of gate-all-around structures within the range of less than 4.3% is smaller than FinFET flip-flops. The simulation results of this paper also help designers to choose a high performance or low power flip-flop design according to their works. In addition, this paper introduces reliable flip-flop circuits for long-term usage in both FinFET and gate-all-around technologies. Temperature and V-DD variation effects on aging analysis approve the efficiency of gate-all-around flip-flops.