Electrostatic Discharge (ESD) and Latchup in 3-D Memory and System on Chip Applications

被引：0
|
作者：
Voldman, Steven H. [1 ]
机构：
[1] Dr Steven H Voldman LLC, S Burlington, VT 05403 USA
来源：
2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Electrostatic discharge (ESD) protection and latchup issues in three dimensional (3-D) semiconductor chip systems is discussed for the first time. ESD protection in 3-D multi-chip systems will be important for both memory and system-on-chip (SOC) applications. Two types of 3-D semiconductor chips will be discussed; a first version introduces edge wiring, and a second version introduces through silicon vias (TSV). In this paper, a new memory device built using the first commercial CMOS manufacturing technology to employ TSVs will be discussed.
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收藏
页码：788 / 790
页数：3
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