Image processing chip for small object detection

被引:3
|
作者
LeRiguer, E
Woods, R
Ridge, D
McCanny, J
机构
[1] Queens Univ Belfast, Sch Elect Engn & Comp Sci, Belfast BT9 5AH, Antrim, North Ireland
[2] Short Brothers, Belfast, Antrim, North Ireland
来源
关键词
D O I
10.1049/ip-cds:19990120
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new, front-end image processing chip is presented for real-time small object detection. It has been implemented using a 0.6 mu, 3.3V CMOS technology and operates on 10-bit input data at 54 megasamples per second. It occupies an area of 12.9mm x 13.6mm(including pads), dissipates 1.5W, has 92 I/O pins and is to be housed in a 160-pin ceramic quarter flat-pack. It performs both one- and two-dimensional FIR filtering and a multilayer perceptron (MLP) neural network function using a reconfigurable array of 21 multiplication-accumulation cells which corresponds to a window size of 7 x 3. The chip can cope with images of 2047 pixels per line and can be cascaded to cope with larger window sizes. The chip performs two billion fixed point multiplications and additions per second.
引用
收藏
页码:49 / 54
页数:6
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