Hardware Design and Implementation of Classic McEliece Post-Quantum Cryptosystem Based on FPGA

With the development of information age, the security of data transmission has attracted more attention. In addition, quantum computers pose a great threat to widely used cryptography algorithms. Therefore, Classic McEliece algorithm is a post-uantum algorithm, which has high security and stands firm in all kinds of attacks for decades. The wide application of the cryptosystem is inseparable from its hardware implementation scheme. So this paper proposes a Classic McEliece implementation scheme based on FPGA platform. To achieve the balance between resources and speed, a variety of methods to implement the scheme are adopted. First, using the characteristics of random access in the RAM, the clock cycle consumption of the error vector generating module is reduced by 95.1%. Second, multiple computing units are employed inside the module for parallel computing and which reduces the number of computing cycles by about 22.4 %. Finally, this thesis proposes a multiplexing syndrome decoding module, and compared to the non-multiplexing scheme, the LUT resource consumption of this thesis is reduced by about 24.2%, and the FF resource consumption of this thesis is reduced by about 15.4%.