Input Dependent Clock Jitter in High Speed and High Resolution ADCs

被引：0

作者：

Chegeni, Amin ^{[1
]}

Shayanfar, Reza ^{[1
]}

Hadidi, Khayrollah ^{[1
]}

Khoei, Abdollah ^{[1
]}

机构：

[1] Urmia Univ, Microelect Res Lab, Orumiyeh, Iran

来源：

2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) | 2012年

关键词：

ADC; input dependent clock jitter; high speed; high resolution; mathematical analysis; ANALOG MOS SWITCHES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the input dependent clock jitter in high speed and high resolution ADCs with a different approach as compared to previous works. There is always a capacitive coupling between the input and the clock signal paths through which the input voltage variation influences the clock and consequently produces jitter even if the sample and hold is assumed ideal and the clock itself is jitter-free. This phenomenon has been analyzed mathematically and then evaluated by simulations. Also the effect of the jitter on the output data has been explained. Results show that for high sampling rate more than 200 MHz this effect dominates and limits the SNR.

引用

页数：4

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