Design and Implementation of A High Resolution DPWM Based on A Low-Cost FPGA

被引：0
|
作者：
Ge, Lu-Sheng [1 ]
Chen, Zong-Xiang [1 ]
Chen, Zhi-Jie [1 ]
Liu, Yan-Fei [1 ,2 ]
机构：
[1] Anhui Univ Technol, Sch Elect Engn & Informat, Maanshan 243002, Anhui, Peoples R China
[2] Queens Univ, Dept Elect & Comp Engn, Kingston, ON K7L 3N6, Canada
来源：
2010 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION | 2010年
基金：
中国国家自然科学基金;
关键词：
DPWM; FPGA; high resolution; adder delay line; PULSE-WIDTH MODULATOR; TIME RESOLUTION;
D O I：
暂无
中图分类号：
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号：
0807 ; 0820 ;
摘要：
This paper proposes a new implementation method which can achieve DPWM with time resolution under 100ps. Utilizing the carry flag delay time, a high resolution DPWM can be achieved by low cost FPGA. The proposed DPWM method is, in principle, intended for FPGA implementation, but it can achieve high time resolution DPWMS and can be implemented in low cost FPGA. Linearity was manually optimized using the presented technique which reduces the non-linearity error. The proposed DPWM with 15-bit and 70-80ps resolution with a switching frequency of 1 MHz has been successfully implemented on a low-cost Atera Cyclone-II series FPGA.
引用
收藏
页码：2306 / 2311
页数：6
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