A 6-b 4-GSPS Low-Voltage Flash ADC with a Pipelined DCVSPG Logic Encoder

被引：0

作者：

Wang, Mingzhen ^{[1
]}

Zhao, Zhou ^{[1
]}

Zhang, Jun ^{[1
]}

Xu, Can ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu 611731, Sichuan, Peoples R China

来源：

2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PROBLEM-SOLVING (ICCP) | 2013年

关键词：

A/D CONVERTER; CMOS;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A 6-b 4-Gsps Flash ADC with a pipelined DCVSPG logic encoder implemented in 0.13 mu m digital process is reported. With ultra-high speed invertor comparators, the clocked DCVSPG encoder with Gray coding lets the ADC achieve 5.4 bits of ENOB at 11.7Mhz input signal and 4-GSPS, 1.1 Ghz of ERBW, 28mW of power consumption with 1.2v power supply, 0.088mm(2) of area size, and 0.17pJ/conv. of FoM. The proposed ADC is suitable for SoC applications.

引用

页码：67 / 70

页数：4

共 4 条

[1] A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder
Radhakrishnan, S
Wang, MZ
Chen, CIH
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[2] A 1.6 GS/s 3.17 mW 6-b Passive Pipelined Binary-Search ADC with Memory Effect Canceller and Reference Voltage Calibration
Tanaka, Koki
Saito, Ryo
Ishikuro, Hiroki
[J]. ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC), 2015, : 327 - 330
[3] Low-power 4-b 2.5-GSPS pipelined flash analog-to-digital converter in 130-nm CMOS
Wang, Mingzhen
Chen, Chien-In Henry
Radhakrishnan, Shailesh
[J]. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2007, 56 (03) : 1064 - 1073
[4] A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H
Neshani, Sara
Azhari, Seyed Javad
[J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2013, 22 (08)

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