A VLST architecture design of VLC encoder for high data rate video/image coding

被引：0
|
作者：
Chang, HC [1 ]
Chen, LG [1 ]
Chang, YC [1 ]
Huang, SC [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, DSP IC Design Lab, Taipei 10764, Taiwan
来源：
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4: IMAGE AND VIDEO PROCESSING, MULTIMEDIA, AND COMMUNICATIONS | 1999年
关键词：
VLSI architecture; VLC; video/image coding;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An efficient architecture of variable length coding (VLC) is developed for recently multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications.
引用
收藏
页码：398 / 401
页数：2
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