Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

被引:31
|
作者
Choi, Gyunghyun [1 ]
Kim, Sung-Hee [1 ]
Ha, Chunghun [2 ]
Bae, Suk Joo [1 ]
机构
[1] Hanyang Univ, Dept Ind Engn, Seoul 133791, South Korea
[2] Hongik Univ, Sch Informat & Comp Engn, Seoul, South Korea
关键词
spatial defects; neural network; pattern recognition; similarity; wafer map; yield management; NEURAL-NETWORK APPROACH; SPATIAL-PATTERN; BIN MAP; YIELD; CLASSIFICATION; FABRICATION;
D O I
10.1080/00207543.2011.574502
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.
引用
收藏
页码:3274 / 3287
页数:14
相关论文
共 50 条
  • [1] An Improved ART1 Neural Network Algorithm for Character Recognition
    Peng Li
    Ma Xianxi
    2010 CHINESE CONTROL AND DECISION CONFERENCE, VOLS 1-5, 2010, : 2946 - 2949
  • [2] Detection and classification of defect patterns on semiconductor wafers
    Wang, Chih-Hsuan
    Kuo, Way
    Bensmail, Halima
    IIE TRANSACTIONS, 2006, 38 (12) : 1059 - 1068
  • [3] Defect cluster recognition system for fabricated semiconductor wafers
    Ooi, Melanie Po-Leen
    Sok, Hong Kuan
    Kuang, Ye Chow
    Demidenko, Serge
    Chan, Chris
    ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE, 2013, 26 (03) : 1029 - 1043
  • [4] A Multi-step Approach for Identifying Unknown Defect Patterns on Wafer Bin Map
    Shin, Jin-Su
    Lee, Dong-Hee
    INDUSTRIAL ENGINEERING AND APPLICATIONS-EUROPE, ICIEA-EU 2024, 2024, 507 : 213 - 226
  • [5] A Multi-Step Reinforcement Learning Algorithm
    Zhang, Zhicong
    Hu, Kaishun
    Huang, Huiyu
    Li, Shuai
    Zhao, Shaoyong
    FRONTIERS OF MANUFACTURING AND DESIGN SCIENCE, PTS 1-4, 2011, 44-47 : 3611 - 3615
  • [6] Generation and motion of dislocations in silicon wafers subjected to multi-step annealing
    Mezhennyi, MV
    Mil'vidskii, MG
    Reznik, VY
    Falster, RJ
    JOURNAL OF PHYSICS-CONDENSED MATTER, 2002, 14 (48) : 12909 - 12915
  • [7] Multi-step Radiographic Segmentation ofWeld Defect Images
    Sowmyalakshmi, R.
    Padmanaban, M. R. Anantha
    Girirajkumar, S. M.
    Benazir, S.
    Farzana, A.
    ADVANCES IN ADDITIVE MANUFACTURING AND JOINING, AIMTDR 2018, 2020, : 409 - 419
  • [8] Multi-Step Mechanical and Thermal Homogenization for the Warpage Estimation of Silicon Wafers
    Xiang, Zhouyi
    Chen, Min
    Deng, Yonghui
    Huang, Songhua
    Liu, Sanli
    Li, Ji
    MICROMACHINES, 2024, 15 (03)
  • [9] Multi-step truncated Q learning algorithm
    Chen, SL
    Wu, HZ
    Han, XL
    Xiao, L
    PROCEEDINGS OF 2005 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-9, 2005, : 194 - 198
  • [10] An improved ART1 neural network learning algorithm
    Sang, Qingbing
    Yin, Ying
    DCABES 2006 PROCEEDINGS, VOLS 1 AND 2, 2006, : 808 - 811