Performance enhancement of partially and fully depleted strained-SOI MOSFETs

被引：14

作者：

Numata, T ^{[1
]}

Irisawa, T

Tezuka, T

Koga, J

Hirashita, N

Usuda, K

Toyoda, E

Miyamura, Y

Tanabe, A

Sugiyama, N

Takagi, S

机构：

[1] Assoc Super Adv Elect Technol ASET, MIRAI, Kawasaki, Kanagawa 2128582, Japan

[2] Toshiba Ceram Co Ltd, Kawasaki, Kanagawa 2128582, Japan

[3] Komatsu Elect Met Co Ltd, Kawasaki, Kanagawa 2128582, Japan

[4] MIRAI, AIST, Kawasaki, Kanagawa 2128582, Japan

[5] Univ Tokyo, Tokyo 1138656, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2006年 / 53卷 / 05期

关键词：

MOSFETs; silicon-germanium (SiGe); silicon-on-insulator (SOI); strained-silicon (strained-Si);

D O I：

10.1109/TED.2006.871871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicongermanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SIO MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gatelength strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.

引用

页码：1030 / 1038

页数：9

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