A Wire Delay Scalable Stream Processor Architecture

Growing on-chip wire delays will cause many future microarchitecture to be distributed. The centralized control and data transmission of the conventional stream processor need to be improved, the hardware resources within a single stream processor become tiles on one or more switched micronetworks. In this paper, we introduce the architecture of the tiled stream processor which aims to adapt to the increasing wire resistance. The tiled stream processor consists of tile arrays, the distributed control and data network which connect tiles. The tile arrays include the five type of reused tiles, the control packet transferred in the control network traverse the tile in a cycle. The architecture of the tiled stream processor supports explicit data management in the hardware way and include two level register hierarchy which are controlled by the software to capture the data locality. The tiled stream processor use the stream programming model which are StreamC/KernelC language, the kernel microcode executed in the tiled arrays are statically scheduled into instruction blocks and execute dynamically in an dataflow order. Finally, we discuss features that affect the kernel performance, with the one cycle routing delay the simulator can achieve an average of 10 IPC in eight kernels.