Design of processor arrays for real-time applications

This paper covers the design of processor arrays for algorithms with uniform dependencies. The design constraint is a limited latency of the resulting processor array. As objective of the design the minimization of the costs for an implementation of the processor array in silicon is considered. Our approach starts with the determination of a set of proper linear allocation functions with respect to the number of processors. It follows the computation of a uniform affine scheduling function. Thereby, a module selection and the size of partitions of a following partitioning is determined. A proposed linearization of the arising optimization problems permits the application of integer linear programming.