Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process

被引:3
|
作者
Chern, Mason [1 ,2 ]
Lee, Shih-Wei [1 ,3 ]
Huang, Shi-Yu [1 ,4 ]
Huang, Yu [4 ]
Veda, Gaurav [4 ]
Tsai, Kun-Han [4 ]
Cheng, Wu-Tung [4 ]
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan
[2] Realtek Semicond Corp, Res & Dev Ctr, Design Technol Dept DFT PFI, Hsinchu 30013, Taiwan
[3] Phison Elect Corp, Innovat Technol R&D Grp, R&D Div 1, IC Dept 3, Hsinchu, Taiwan
[4] Mentor, Siemens Business A, Tessent Design Silicon, Wilsonville, OR 97070 USA
关键词
Circuit faults; Artificial neural networks; Training; Neurons; Integrated circuits; Indexes; Fault diagnosis; intermittent faults; neural network; stuck-at faults;
D O I
10.1109/TCAD.2019.2957356
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the "candidate set of scan cells for the next round of ANN inference," will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.
引用
收藏
页码:3044 / 3055
页数:12
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