Verification of System LSIs for Image Processing

In recent years, system LSIs have become more complicated in terms of their hardware structure along with their increase in size and greater functions, and this is making it difficult to verify their logic quality. Image-processing LSIs, in particular, have a higher complexity of software processing that they perform with their multi-core structures and increasingly complicated structure of internal buses. This makes it essential to ensure that their functions, performance and power consumption satisfy the requirements by conducting system verification at the pre-silicon stage (LSI design phase). However, product development with a short turnaround time (TAT) is called for because of the recent shorter model change cycles, and efficiently conducting system verification while ensuring quality is very important. Fujitsu Semiconductor is making positive use of a hardware emulator (a device capable of mapping the circuit to be verified to dedicated hardware for running it at high speed) to establish verification technology that ensures quality and improves verification efficiency at the same time, and applying it to product models. This paper presents hardware/software co-verification, performance verification and power consumption estimation by using a hardware emulator, which we believe is very effective for verifying image-processing LSIs.