Memory renaming: Fast, early and accurate processing of memory communication

As processors continue to exploit more instruction level parallelism, greater demands are placed on the performance of the memory system. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load and store instructions to speed the processing of memory traffic. The approach works by accurately predicting memory communication early in the pipeline and then re-mapping the communication to fast physical registers. This work extends previous studies of data value and dependence speculation. When memory renaming is added to the processor pipeline, renaming can be applied to 30-50% of all memory references, translating to an overall improvement in execution time of up to 14% for current pipeline configurations. As store forward delay times grow larger, renaming support can lead to performance improvements of as much as 42%. Furthermore, this improvement is seen across all memory segments-including the heap segment which has often been difficult to manage efficiently.