State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction

被引:3
|
作者
Guo, Yang [1 ]
Qu, Wanxia [2 ]
Zhang, Long [1 ]
Xu, Weixia [2 ]
机构
[1] Natl Univ Def Technol, Inst Microelect & Microprocessor, Sch Comp Sci, Changsha, Hunan, Peoples R China
[2] Natl Univ Def Technol, Inst Comp, Sch Comp Sci, Changsha, Hunan, Peoples R China
来源
JOURNAL OF SUPERCOMPUTING | 2012年 / 62卷 / 02期
基金
中国国家自然科学基金;
关键词
Parameterized cache coherence protocol; True concurrency; Model checking; Two-dimensional abstraction; ENVIRONMENT ABSTRACTION; VERIFICATION;
D O I
10.1007/s11227-012-0755-0
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Scalability of cache coherence protocol is a key component in future shared-memory multi-core or multi-processor systems. The state space explosion is the first hurdle while applying model-checking to scalable protocols. In order to validate parameterized cache coherence protocols effectively, we present a new method of reducing the state space of parameterized systems, two-dimensional abstraction (TDA). Drawing inspiration from the design principle of parameterized systems, an abstract model of an unbounded system is constructed out of finite states. The mathematical principles underlying TDA is presented. Theoretical reasoning demonstrates that TDA is correct and sound. An example of parameterized cache coherence protocol based on MESI illustrates how to produce a much smaller abstract model by TDA. We also demonstrate the power of our method by applying it to various well-known classes of protocols. During the development of TH-1A supercomputer system, TDA was used to verify the coherence protocol in FT-1000 CPU and showed the potential advantages in reducing the verification complexity.
引用
收藏
页码:828 / 854
页数:27
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