Micropipeline architecture for multiplier-less FIR filters

被引：0
|
作者：
Nooshabadi, S
MontielNelson, JA
Visweswaran, GS
Nagchoudhurhi, D
机构：
来源：
TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/ICVD.1997.568175
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropiplined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.
引用
收藏
页码：451 / 456
页数：6
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