Auto-optimizing Bus Encoding for reduced Power Dissipation in Dynamically Reconfigurable Hardware

被引：0

作者：

Kretzschmar, C ^{[1
]}

Siegmund, R ^{[1
]}

Müller, D ^{[1
]}

机构：

[1] Chemnitz Univ Technol, Dpt Syst & Circuit Design, D-09126 Chemnitz, Germany

来源：

ERSA 2001: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS | 2001年

关键词：

low power; transition minimizing bus encoding; dynarnic reconfiguration;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

lit this paper an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to auto-minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 44 %.

引用

页码：71 / 77

页数：7

共 10 条

[1] Low Power Encoding Techniques for Dynamically Reconfigurable Hardware
Claudia Kretzschmar
Robert Siegmund
Dietmar Müller
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[J]. JOURNAL OF SUPERCOMPUTING, 2003, 26 (02): : 185 - 203
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[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (03) : 508 - 526
[10] The design and fabrication of a reconfigurable hardware testbed for the interaction analysis of power converters in a reduced-scale Navy DC distribution system
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