A Digitally Configurable Receiver for Multi-Constellation GNSS

This paper presents the design, implementation, and performance evolution of a Digitally Configurable Receiver (DCR) that is capable of tracking civilian GPS L1/L2C and GLONASS G1/G2 signals. A hardware/software co-design approach is adopted in the proposed receiver to provide an easy access to modify at will the receiver parameters such as RF gain, position update rate, correlator spacing, code/carrier loop noise bandwidth, and discriminator type. The digital Intermediate Frequency (IF) signal at the output of the Analog-to-Digital (A/D) converter is down-sampled by the Virtex-5 FPGA and sent to the Linux workstation via high-speed PCI Express (PCIe) link to perform Parallel Code Phase Search (PCPS) acquisition to enable a fast signal acquisition procedure. The results for the code offset and carrier frequency obtained from the acquisition engine are used to initialize the code and carrier Numerically Controlled Oscillators (NCOs). There are 64 tracking channels implemented on the FPGA, which are driven by the RF front-end's master Chip-Scale Atomic Clock (CSAC). This setup provides two highly synchronous receivers. As the receiver is tailor-made for high-end research applications, the outputs of the correlator arms, code and carrier error, C/N0, navigation data, and RINEX output is available to the end-user. The resulting receiver is capable of acquiring and tracking all visible satellites with an elevation angle of 5 degrees or more and with Carrier-to-Noise Ratio (C/N-0) in the range of 47 to 37dB-Hz.