FPGA Implementaion of FEC for 10G-EPON

被引：0
|
作者：
Li, Xicong [1 ]
Cao, Yinying [1 ]
Chen, Xue [1 ,2 ]
Gao, Weidong
机构：
[1] State Key Lab Informat Photon & Opt Commun BUPT, POB 128, Beijing 100876, Peoples R China
[2] GW Delight Technol Co Ltd, Beijing 100085, Peoples R China
来源：
2012 ASIA COMMUNICATIONS AND PHOTONICS CONFERENCE (ACP) | 2012年
关键词：
D O I：
暂无
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
New parallel RS(255,223) encoder and decoder architectures for 10G EPON FEC are presented and realized in FPGA. The proposed architectures can operate at 156.25MHz to achieve the throughput of 10.3125Gbps with small hardware-complexity and low latency. (C) 2012 Optical Society of America
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页数：3
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