Accelerating block-matching and 3D filtering-based image denoising algorithm on FPGAs

Image denoising is an important pre-processing step in the field of computer vision. And the block-matching and 3D filtering (BM3D) algorithm has achieved quite impressive results in the terms of denoising quality, but it is not being widely used due to its computational complexity. In this paper, we consider FPGA as accelerator because of its reconfigurability and advantage on energy efficiency over GPU. We present a OpenCL-Based FPGA implementation which increased the image processing speed significantly. At the same time, the denoising quality of the image is not affected too much. To our knowledge, this is the first successful attempt of the BM3D algorithm on FPGAs. Also, our implementation is more fine-grained partition of the algorithm, so some parts of our algorithmic, such as block-matching, can be utilized separately to other similar algorithms.