A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique

被引:3
|
作者
Jin, Jahoon [1 ]
Kim, Seok [2 ,3 ]
Jin, Xuefan [1 ]
Kim, Sang-Hoon [1 ]
Chun, Jung-Hoon [1 ]
机构
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea
[2] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea
[3] Elect & Telecommun Res Inst, Daejeon 34044, South Korea
关键词
AC-coupled equalization (EQ); adaptive equalization; dual-loop clock and data recovery (CDR); finite-impulse response (FIR); high-speed interface; intersymbol interference (ISI); near ground; timing margin; transceiver; voltage mode; ADAPTIVE EQUALIZATION; DATA RECOVERY; CMOS;
D O I
10.1109/TVLSI.2017.2773642
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (CTLE) on the receiver (RX) side compensates for the channel attenuation. Based on the maximum eye algorithm, the peaking gain of CTLE is adaptively controlled to track a time-variant environment, such as PVT variations. Each TX and RX is implemented with clocking circuits: a differential PLL, and a dual-loop clock and data recovery circuit. The proposed transceiver is fabricated in a 45-nm CMOS process, and the entire TX and RX, respectively, consume 92 and 138 mW under a 1.2-V supply while operating at 12.5 Gb/s.
引用
收藏
页码:522 / 530
页数:9
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