An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators

被引：5
|
作者：
Zhang, Yang [1 ]
He, Xiaoyong [2 ]
Pun, Kong-Pang [1 ]
机构：
[1] Chinese Univ Hong Kong, Dept Elect Engn, Hong Kong, Peoples R China
[2] South China Univ Technol, Guangzhou, Guangdong, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 03期
关键词：
Multi-level DAC; delta-sigma modulator; PWM; element mismatches; ADC;
D O I：
10.1109/TCSII.2018.2859776
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The nonlinearity of the multi-level digital-to-analog converter (DAC), arising from element mismatches, is a critical issue in the design of multi-bit Delta-Sigma modulators (DSMs). In this brief, we propose an extremely linear multi-level DAC that requires no trimming, calibration, or dynamic element matching for continuous-time DSMs that are sensitive to loop delays. The proposed DAC combines a tri-level switched-capacitor circuit with a pulse-width-modulation (PWM) scheme modified to eliminate the nonlinearity-causing signal-dependent timing of the PWM pulses. Theoretical analysis and Monto-Carlo simulations verifying the linearity of the proposed DAC are presented.
引用
收藏
页码：367 / 371
页数：5
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