HTS surface-modified junctions with integrated ground-planes for SFQ circuits

被引：0
|
作者：
Soutome, Y [1 ]
Fukazawa, T [1 ]
Saitoh, K [1 ]
Tsukamoto, A [1 ]
Takagi, K [1 ]
机构：
[1] Hitachi Ltd, Adv Res Lab, Kokubunji, Tokyo 1858601, Japan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2002年 / E85C卷 / 03期
关键词：
high-temperature-superconductor; Josephson junction; SEQ circuit; ramp-edge junction; groundplane;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a I-sigma spread in the critical current of 7.9% for 100 junctions at 4.2K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.
引用
收藏
页码：759 / 763
页数：5
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