Modeling the Impact of TSVs on Average Wire Length in 3DICs using a Tier-Level Hierarchical Approach

In a 3-dimensional integrated circuit (3DIC) the active tiers are interconnected using top-metal layer micro-bumps or through-silicon-vias (TSVs). The active area occupied by a TSV is typically several times larger than that of a gate and cannot be ignored while estimating average wire length. Additionally, the Rents rule parameters used in modeling may not be the same for all tiers, especially when a 2DIC design is modified for 3DIC implementation, or when diverse logic circuits at different technology nodes are stacked into a single 3DIC. Hence, a tier-by-tier hierarchical wire-length distribution estimation method is introduced that can also be applied for cases of different Rents parameters for each tier. Moreover the model can handle variable TSV dimensions and different bonding techniques. It also provides an upper bound estimate on the number of TSVs, above which the resulting average wire length degrades. Several experimental results are presented to demonstrate the utility of the proposed model. Results show that a slight difference in the Rents exponent (about 0.01) between tiers and different TSV sizes have significant effects on 3DIC average wire length. Additionally, the face-to-back bonding method results in a higher upper bound (1.9x to 2.2x) than back-to-back bonding for a two-tier 3DIC.