A Novel Quasi-3-D Threshold Voltage Model for Fully Depleted Quadruple-Gate (FDQG) MOSFETs: With Equivalent Number of Gates (ENG) Included

被引:24
|
作者
Chiang, Te-Kuang [1 ]
机构
[1] Natl Univ Kaohsiung, Dept Elect Engn, Adv Devices Simulat Lab, Kaohsiung 81148, Taiwan
关键词
DIBL; double-gate (DG) MOSFETs; natural length; quadruple-gate (QG) MOSFETs; quasi-3-D scaling equation; threshold voltage roll-off; DEVICE DESIGN GUIDELINES; SOI MOSFETS;
D O I
10.1109/TNANO.2013.2284013
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Instead of solving the three-dimensional (3-D) Poisson's equation, we present a novel quasi-3-D threshold voltage model for fully depleted quadruple-gate (QG) MOSFETs based on the minimum central potential derived from the quasi-3-D scaling equation. Accounting for short-channel effects (SCEs) on the device, the natural length of the QG FET in the scaling equation is obtained from the equivalent number of gate equation of 1/lambda(2)(QG) = 1/lambda(2)(DG1) + 1/lambda(2)(DG2), where the QG device working in x-y-z space with natural length of lambda(QG) can be broken into two equivalent double-gate (DG) FETs with natural lengths of lambda(DG1) and lambda(DG2) working in y-z and x-z planes, respectively. Numerical simulation data for threshold voltage roll-off and drain-induced barrier lowering effects (DIBL) were compared to the model to validate the formula. Among QG FETs with the same perimeters, one with a square cross section will show the worst immunity to SCEs due to the largest natural length. With the criterion of DIBL <= 50 mV, an improvement of up to 30% is illustrated in the minimum channel length for the QG MOSFET in comparison to the DG MOSFET.
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页码:1022 / 1025
页数:4
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