Hysteresis caused by defects in buffer layer of metal ferroelectric-insulator-semiconductor (MFIS) devices

We have investigated the roles of buffer layer in the Pt/SBT-Y2O3/p-Si (MFIS) capacitors. We found that the insertion of Y2O3 buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However. negative charges with the effective density of 3.21 x 10(12)/cm(2) were generated due to the additional process step for Y2O3 deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y2O3 buffer layer minimize the charge injection. the shift of the hysteresis loops was asymmetrical.