A Fine-grained Analysis and ASIP Design Strategy for Specific Algorithm

An effective ASIP design strategy utilizing fine-grained code profiling is presented for specific algorithm. The fine-grained profiler combining the merits of high level and assembly level profiling methods provides sufficient characteristics of target algorithm to design instruction set architecture (ISA) of ASIP. The general design strategy includes converting the target algorithm into simple code blocks, taking fine-grained analysis, and extending custom instructions (CI). Architecture of coupling hardware is designed to implement the extended instructions, which are appended as co-processor. As an instance, Secure Hash Algorithm (SHA) is taken as the target code, to design an ASIP in this process. The implementation result shows that the designed processor has, at expense of relatively small hardware area consumed, achieved obvious improvement of performance.