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- [1] Defect Tolerant Approaches for Function Mapping in Nano-Crossbar Circuits 2018 FOURTH IEEE INTERNATIONAL CONFERENCE ON RESEARCH IN COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (ICRCICN), 2018, : 48 - 53
- [2] A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2018, 4 (04): : 522 - 532
- [5] Yield Analysis of Nano-Crossbar Arrays For Uniform and Clustered Defect Distributions 2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 534 - 537
- [7] Application-independent defect-tolerant crossbar nano-architectures IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, : 898 - 902
- [8] Runtime Analysis for Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures 2009 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES, 2009, : 75 - 78
- [9] Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE VLSI SYSTEMS, PROCEEDINGS, 2009, : 322 - 330
- [10] Defect Tolerance in Diode, FET, and Four-Terminal Switch Based Nano-Crossbar Arrays PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15), 2015, : 82 - 87