Optimized 25V, 0.34m Omega center dot cm(2) very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process

The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R(sp)) at the 20V node. The 20V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19V in planar devices. Here the structure performance is advanced by optimizing a Very-Thin-RESURF (VTR) region (VTR Xj=0.3 mu m). This work presents a planar VTR drain extended IGFET with best case BV=25V and R(sp)=0.34 m Ohm . cm(2) @ V-gs=1OV using a compressed BiCMOS VLSI, 1 mu m technology. Structure variation and thermal performance are characterized.