An Energy-Efficient Accelerator for Hybrid Bit-width DNNs

This paper proposed an energy-efficient accelerator for hybrid bit-width DNNs. To speedup the DNNs and make it energy-efficient, we first propose a hybrid bit-width compression method that can save the memory storage of the state-of-the-art network LeNet and AlexNet by 7x and 8x with negligible accuracy loss. Also we propose an energy-efficient iterative logarithmic multiplier with approximate computing to process the multiply-accumulate operations for DNNs. The computational ability and adaptability of the FPGA greatly expands by using the LUT-based multiplier with improved iterative logarithmic rather than a DSP-based multiplier. The accelerator power is reduced from 24.1 W to 14.3 W. The accelerator proposed performs 1.53 times better in power efficiency and can achieve 33.98 GOP/s/W comparing with state-of-the-art architecture.