Low-power Optimization of DAU Master Node in Large-Scale Seismic Instrument

被引:0
|
作者
Zhao Rui-xiang [1 ]
Ma Cheng [1 ]
Xiong Jiang-ping [1 ]
Ja Hui-bo [1 ]
机构
[1] Tsinghua Univ, Key Lab Precis Measurement Technol & Instruments, Beijing 100084, Peoples R China
关键词
Seismic instrument; power optimization; FPGA;
D O I
暂无
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
This paper introduces a low-power optimization design to solve the power consumption problem of large-scale seismic instrument. Through improving power performances of data transmission, power supplement, data coding and decoding as well as clock management, the new design of DAU (digital acquisition unit) master node cuts the power consumption by 34%. The field survey showed that the low-power version extended the instrument service life and increased the crew efficiency.
引用
收藏
页码:296 / 301
页数:6
相关论文
共 5 条
  • [1] Chandrakasan A. P, 1992, LOW POWER TECHNIQUES
  • [2] Chandrakasan AnanthaP., 1992, Low-Power CMOS Digital Design
  • [3] Devadas S, 1990, ESTIMATION POWER DIS
  • [4] JIA Huibo, 2010, China Patent, Patent No. [101764617A, 101764617]
  • [5] Yan Zhang, 2006, CLOCK GATING FPGAS N, P584