Architecture and Design of the AGIPD Detector for the European XFEL

被引:0
|
作者
Becker, J. [1 ]
Bianco, L. [1 ]
Goettlicher, P. [1 ]
Graafsma, H. [1 ]
Hirsemann, H. [1 ]
Jack, S. [1 ]
Klyuev, A. [1 ]
Marras, A. [1 ]
Trunk, U. [1 ]
Klanner, R. [2 ]
Schwandt, J. [2 ]
Zhang, J. [2 ]
Dinapoli, R. [3 ]
Greiffenberg, D. [3 ]
Henrich, B. [3 ]
Mozzanica, A. [3 ]
Schmitt, B. [3 ]
Shi, X. [3 ]
Gronewald, M. [4 ]
Krueger, H. [4 ]
机构
[1] DESY, Notkestr 85, Hamburg, Germany
[2] Univ Hamburg, Hamburg, Germany
[3] PSI, Villigen, Switzerland
[4] Univ Bonn, Bonn, Germany
关键词
XFEL; 2D detector; Hybrid Pixel Detector;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
AGIPD is a hybrid pixel detector developed by DESY, PSI, the University of Bonn and the University of Hamburg. The detector is targeted for use at the European XFEL, a source with unique properties: a bunch train of 2700 pulses with > 10(12) photons of 12 keV each, only 100 fs long and with a 220 ns spacing, is repeated at a 10 Hz rate. This puts up very demanding requirements: dynamic range has to cover the detection of single photons and extend up to > 10(4) photons/pixel in the same image, and as many images, as possible have to be recorded in the pixel to be read out between pulse trains. The high photon flux impinging on the detector also calls for a very radiation hard design of sensor and ASIC. The detector will consist of 16 Sensor modules arranged around a central hole for the direct beam. Each made of a single sensor bump-bonded to 2 X 8 readout chips of 64 X 64 pixels in a grid of 200 mu m m pitch. Each pixel of these ASICs contains a charge sensitive preamplifier featuring adaptive gain switching, changing sensitivity in three ranges, and a buffer to provide correlated double sampling ( in the highest sensitivity mode). Most of the pixel area, albeit, is used for an analogue memory to record 352 frames. It is operated in random-access mode: data containing bad frames can be overwritten and the memory can be used in the most efficient way. The readout between two bunch trains is arranged via 4 ports: Data from pixels of one row is read in parallel and serialised by 4 multiplexers at the end of the pixel columns and driven off-chip as differential signals. The operation of the ASIC is controlled via a three-line serial interface, using a command based protocol. It is also used to configure the chip's operational parameters and internal timings.
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页码:585 / 590
页数:6
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