High Frequency Power Integrity Design Sensitivity to Package Design Rules

被引：0
|
作者：
Shekhar, Sameer [1 ]
Jain, Amit K. [1 ]
Kuan, Chin Lee [2 ]
机构：
[1] Intel Corp, Hillsboro, OR 97124 USA
[2] Intel Microelect M Sdn Bhd, George Town 11900, Malaysia
来源：
2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC) | 2018年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Package design rules are traditionally determined by signal integrity reasons. However, these determine the total package inductance and the number of capacitors that can be installed, in turn determining the highest frequency impedance peak in the power delivery network. This paper provides an overview of design rule impact to electrical metrics. Simple equations and simulations based on electromagnetic extractions of representative microprocessor packages are utilized throughout. Based on these guidelines are provided for capacitor spacing and PTH size & placement evaluation as logic block sizes shrink with process node advancement.
引用
收藏
页码：266 / 269
页数：4
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