Verification of a Calibration Method for Digital to Analog Converters

被引：0
|
作者：
Marin, Mihai-Eugen [1 ]
Constantinescu, Florin [1 ]
Brinzei, Catalin [2 ]
Gheorghe, Alexandru [1 ]
机构：
[1] Univ Politehn Bucuresti, Dept Elect Engn, Bucharest, Romania
[2] Infineon Technol Romania SCS, Bucharest, Romania
来源：
2016 INTERNATIONAL SYMPOSIUM ON FUNDAMENTALS OF ELECTRICAL ENGINEERING (ISFEE) | 2016年
关键词：
Calibration methods; digital to analog converters; high speed DAC; SFDR;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new calibration method for digital to analog converters (DAC) is verified, measuring a set of chips, each containing a 8 bit current steering DAC with a 5+3 segmented architecture. For a sampling frequency of 500MHz and a bandwidth of 5MHz all tested circuits exhibited, after calibration, a Spurious Free Dynamic Range (SFDR) better than 50dB. For a sampling frequency of 1GHz and a bandwidth of 10MHz, a SFDR better than 40dB resulted for all tested cases. These last results could be explained by a degradation of the digital signal supplied by the FPGA board, which has a maximum reliable clock frequency of 600MHz, and by the influence of the parasitic elements introduced by the PCB traces. In all measured cases an improvement of 2-4dB of the SFDR value has been obtained using the proposed calibration method.
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页数：5
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