Time-based all-digital sigma-delta modulators for nanometer low voltage CMOS data converters

A phase-based delta-sigma (Delta Sigma) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed Delta Sigma ADC achieved 50.5 dB SNDR or 8.09 bits resolution for a 10 MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL-DCDL) as the phase-domain counterparts of an ADC-DAC in a traditional delta-sigma modulator. Simulation results of the new modulator achieve a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth.