Back-gate bias effect on UTBB-FDSOI non-linearity performance

被引：0

作者：

Esfeh, B. Kazemi ^{[1
]}

Kilchytska, V. ^{[1
]}

Parvais, B. ^{[2
,3
]}

Planes, N. ^{[4
]}

Haond, M. ^{[4
]}

Flandre, D. ^{[1
]}

Raskin, J. -P. ^{[1
]}

机构：

[1] Catholic Univ Louvain, ICTEAM, B-1348 Louvain La Neuve, Belgium

[2] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[3] Vrije Univ Brussel, Dept Elect & Informat ETRO, Pl Laan 2, B-1050 Brussels, Belgium

[4] ST Microelectron, ST, 850 Rue J Monnet, F-38926 Crolles, France

来源：

2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2017年

关键词：

Fully depleted (FD) SOI; MOSFETs; non-linearity; harmonic distortion; measurements;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work investigates experimentally the nonlinearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the nonlinearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of "effective body factor" and lesser mobility degradation with increase of the positive backgate bias.

引用

页码：148 / 151

页数：4

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